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Pages: 1 questvlsi member Reged: 07/24/07 Posts: 1 Loc: Bangalore/Karnataka/India SystemVerilog - Passing class through mailbox       #3688 - 08/07/07 08:27 AM (125.17.142.34) Edit   Reply   Quote   Quick Reply   Hello All, Iam not sure is this the correct forum to post this question since its related to Modelsim6.3a iam posting here. Iam trying to put a class inside Mailbox, there is no compilation error in Modelsim6.3a but when i executing vsim its not getting simulated properly. There is a simulation error happening. But the same code is getting compiled in ncverilog, is this a limitation of Modelsim6.3a, i have given the code below for reference. <code> program test(); class test; rand i; randc j; endclass mailbox mbx; test t1; initial begin mbx = new; t1 = new; assert (t1.randomize()); mbx.put(t1); // Simulation error at this point endprogram </code> Can any one let me know how i can pass class through mailbox using Modelsim6.3a QuestVlsi Post Extras:       shaohao member Reged: 08/29/07 Posts: 3 Loc: Shanghai, China Re: SystemVerilog - Passing class through mailbox [Re: questvlsi]       #3770 - 08/29/07 10:42 AM (218.81.105.201) Edit   Reply   Quote   Quick Reply   mailbox #(test) mbx; Post Extras:       Pages: 1

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