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Pages: 1 sumanthhv member Reged: 04/26/10 Posts: 1 Loc: Karnataka/India regarding current state display in vhdl and vlog       #7060 - 04/26/10 01:25 AM (59.160.207.20) Edit   Reply   Quote   Quick Reply   dear forum users, since we declare state machine as an enumerated data type in vhdl, we get to see the name of the current state the state machine is in. But, in verilog, such a thing is not possible. Eventhough, we declare each state as a parameter, in simulation, the parameter's value is displayed but not the parameter's name. Is there a workaround for this? can we force the simulator to display the parameter's name instead of its value? thanks in advance, Sumanth Post Extras:       JM_Williams member Reged: 10/30/06 Posts: 2 Loc: California Re: regarding current state display in vhdl and vlog [Re: sumanthhv]       #7061 - 04/26/10 05:45 PM (71.131.26.150) Edit   Reply   Quote   Quick Reply   I don't think there is any easy way to see the name of the current state in the waveform display. Most simply, you could write a function which uses $display to print the name of the current state, and the simulation time, on every transition. More complexly, you could write a task in the testbench which reads the current state and encodes its name in a wide-enough reg in ASCII characters (7 bits per char); the encoded name then could be displayed in a wave window, showing the state name in the waves in ASCII format. Actually, for performance, the simulator should be enhanced to do this; or, a PLI routine might be written for it. Post Extras:       Pages: 1

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