DavidZar
member
Reged: 09/22/04
Posts: 60
Loc: MO
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This is the DFT forum vote. If there is enough interest a new forum will begin. If you vote "yes" this implies you will post at least one question/solution/tip to the new forum!
If no forum is added, this "general" forum can, and should, be used for such topics.
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David M. Zar
Instructor in Computer Engineering
Washington University in St. Louis
Edited by DavidZar (01/25/05 08:24 AM)
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Jack
member
Reged: 11/02/04
Posts: 44
Loc: Chicago
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If you want to discuss something about DFT,
why don't you just start?
I will help if I can...
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(see JaxHead)
.
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richa2
member
Reged: 02/04/05
Posts: 2
Loc: India
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Hi,
I have an ASIC whose 7 scan chains have some snags but which works fine on functional board validation. To get a coverage on the flops covered by these 7 scan chains, I am using a vcd file to feed in functional vectors but fault simulation in flextest is proceeding very slowly making the process unfeasible. Is there anybody who has faced a similar issue , is there a way to speed up Flex test fault simulation run drastically or any other way out to target the flops where scan is apparent malfunctioning? Any help would be deeply appreciated.
Thanks,
Richa
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Mike_R_Jones
member
Reged: 11/02/04
Posts: 10
Loc: Aloha Oregon
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Hi Rich,
I will be glad to help. Flextest yes is slow. Because it has to do more than
event simulation and Flextest is designed for functional pattern generation.
I just happens to be able to do fault simulation at the same time. That said
here are the basics for performance. The factors that determine practical
use are as follows.
Number of gates < 2 million on a big machine is about a upper pain limit.
Number of RAM in the design. If you know how these will be initialized it
is best to avoid programing these via patterns and load the data directly.
Number of Loops. By all means controlling these is a good thing. This includes loops that flow though rams, Bidir pins and functional loop.
Rams can be control with enables to top level pins. Bidirs with 'add slow pad'
and functional loops with test points.
The number of test cycles is also a factor. The higher the number the more
work per vector.
There are a few more things but they are not often encountered.
The best advice is to keep things simple and work up.
I will be glad to help further. Best of success with your project.
And yes I would be interested in a DFT Forum.
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// Mike R. Jones
// Mentor Graphics, DFT Customer Support
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Mike_R_Jones
member
Reged: 11/02/04
Posts: 10
Loc: Aloha Oregon
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Hi Rich,
I was so excited that someone posted that I forgot to think more about
your real question. With broken chains the problems get hard. I would like
to know more about the 'break', perhaps there is another approach. I would
like to know if there is anything that can be salvaged. I assume that the
design is on the ATE, so no design changes?
I hope we can help.
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// Mike R. Jones
// Mentor Graphics, DFT Customer Support
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ChessPlayer
member
Reged: 01/25/05
Posts: 2
Loc: Scotland
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I would certainly vote for a DFT Forum, but perhaps there should be some clear guidelines as to what what the scope of the forum is?
Are we talking about DFT within chip design, or DFT for the board design. It's all very well to have DFT that the designer can use but do we need DFT for the board test engineering in production as well?
It's all very well to create test vectors but I for one would like to advocate re-use beyond the tool set and that are also safe to use in the intended application.
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Mike_R_Jones
member
Reged: 11/02/04
Posts: 10
Loc: Aloha Oregon
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For the Mentor DFT products Fastscan, Flextest and TestKompress the main
focus has been on IC test. However they are not limited to these. The only thing holding back Board level is the size of the total design. We also work
with Boundary Scan and for most of DFT customers, the focus is on IC test.
I am all for guidelines. If we could limit this to Mentor DFT products it would
be good. There are other forums on the other topics.
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// Mike R. Jones
// Mentor Graphics, DFT Customer Support
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Paul
member
Reged: 01/04/05
Posts: 55
Loc: Switzerland
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Quote:
There are other forums on the other topics.
Mike,
could you provide any links to alternative (tool-independent) forums on DfT, please? I know some IC and or PCB design forums, but none on DfT.
Personnally, I believe that discussing general DfT topics in this forum would generate interest of a broader design community and increase the usefulness of the forum and even increase the number of potential customers for MGC. But this is my very personal opinion.
Paul
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ChessPlayer
member
Reged: 01/25/05
Posts: 2
Loc: Scotland
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I agree that we should limit the DFT forum to Mentor products, but I don't think that the sole emphasis on DFT is for the chip design.
My company certainly uses the Mentor product for board design as well as FPGA/CPLD design, does that mean we get dropped out of some of Mentor's DFT initiatives?
Perhaps there is a need to show how the existing chip level tools can be used in some form to apply at least some DFT rules to board design.
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Mike_R_Jones
member
Reged: 11/02/04
Posts: 10
Loc: Aloha Oregon
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The other forums that I had in mind where for timing, simulation and synthesis. For example: http://www.deepchip.com/ .
I do agree that there are no true DFT forums. I for one would like this
to become such.
Further I know that several folks in engineering and marketing are looking
for or can contribute to board level products or FPGA. Since Mentor is in
the field for FPGA tools we are always looking for good applications. The
reality is however FPGA are hard to test 'itself' that is how to get every
function that can be programed in a testable form. Folks in the emulation
group have this issue with incoming inspection before they start using a
box full of IC in their systems. So I for one say lets open this up and
bring on the questions. There are three of our support engineers used
to be in board test manufacturing. So this is not unfamiliar ground.
Best of regards,
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// Mike R. Jones
// Mentor Graphics, DFT Customer Support
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richa2
member
Reged: 02/04/05
Posts: 2
Loc: India
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Hi Mike,
Thanks for the help. The test is on ATE and no design changes are possible. Currently 7 scan chains out of a total of 64 are failing while the equivalent board tests covering this functionally are through. As I had mentioned in my previous post, Flextest is too slow to cover these flops through functional vectors, however is it possible to use sequential ATPG to obtain coverage on the relevant part of the design? I am not familiar with this, so any pointer as to how efficient in terms of coverage and simulation time this approach is,would be really helpful. Please tell me if there are any details which might assist.
Thanks once again,
Rich
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Mike_R_Jones
member
Reged: 11/02/04
Posts: 10
Loc: Aloha Oregon
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Hi Rich,
What you could try is using is Fastscan. The Broken chains are simply masked out. Leave
definition out of the setup command. These are now X sources. What Fastscan will try to do
is to search harder for a pattern to reach a fault. You will likely have to do two things
Increase the sequential depth and the abort limit. Using:
set pattern type -seq N
set abort limit L
Here now comes the question on how big the design is. If this very large > 10 Mill simulation
gates then there will be limits to how big N and L can be. If say this is 4 Mill gates then
on a big machine I would first increase N the depth and use a modest abort limit. Also
the ATPG Expert is really handy. This is started with:
create patterns -auto
This will make selections of the sequential depth and abort limit. I would use this first.
Also I would identify the blocks that the broken chains go to. These should be no faulted
as a first pass. Basically working on the easy faults first. The broken chain area will be
harder to test.
You may get (if not likely) messages that say 'test generator aborted K faults, increase
abort limit'. This means that Fastscan ATPG engine gave up after the abort limit in testing
the faults. These faults have not be proven to be untestable (AU) so they are returned to
the UO fault set for later. Then later with the remaining faults and the broken chain block
added back now increase the depth and abort limit step by step. Now it comes to your
threshold of pain. How long can you wait for patterns. If at any time your coverage reaches
your coverage level you need stop. Note you may have to set new goals for this to meet
minimum business goals.
With luck you may still get the patterns and coverage you need.
--------------------
// Mike R. Jones
// Mentor Graphics, DFT Customer Support
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john84
member
Reged: 06/20/06
Posts: 1
Loc: India
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Good thought Mike....
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abuissa
member
Reged: 05/02/08
Posts: 1
Loc: UK
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Hi
I am a new user to mentor graphics tool. I have the DFT stuff. what I want to do is to get a cube of test vectors that can test a combinational circuit.
i.e. if I have a circuit with 5 inputs for example, I want a group of test vectors that can test all the stuck at faults where the unspecified inputs will be replaced by x (don't care), the output will be something like:
test vector 1: 1x01x
test vector 2: xx001
and so on.
Can you help me step by step how to do this?
Many thanks in advance
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intenso
member
Reged: 07/12/10
Posts: 1
Loc: france
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Hi
I am currently using Mentor graphics testkompress and I have a problem during the generation of my paternal circuit knowing that I generated my IP in a module of my circuit.
exixte there a command that allows you to specify the level of my chip wher I can do the compression ?
Many thanks in advance
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